Senior Analog Layout Engineering - Networking

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Annoncen er udløbet, og stillingen kan ikke længere søges. Opslaget vises udelukkende som reference

What you will be doing

:
  • Strategizing and implementation of high-speed opto-electrical analog layout in state-of-the-art nodes.

  • In close co-operation with the Design Team, review and analyze complex analog schematics for layout implementation.

  • Ensuring that all relevant parasitics are considered and ensuring quality by identifying and verifying device matching, IR drop and electro migration.

  • Potentially planning, ensuring stakeholder management and leading projects from start to finish.

  • What we need to see:

  • Dedication and drive to improve the success of the team.

  • Strong drive and ability to understand the problem and decide on solutions.

  • Systematic approach to planning and execution.

  • A Master’s Degree or equivalent experience in electrical engineering or similar.

  • Minimum of 5 years' experience with Analog IC Layout is required.

  • Ways to stand out of a crowd:

  • Transistor level knowledge for circuits such as TIAs and Optical Drivers.

  • Ability to recognize failure prone circuit and layout structures, good grasp of analog and DFM standard methodologies, and proactivity in working with circuit designers to identify the best approach to solving problems.

  • Knowledge of Mentor, Synopsys or Cadence layout tools.

  • Proactively influence the chip design process by means of automatization and strategizing.

  • Previous responsibility for ramping up new process nodes.

  • Skriv i din ansøgning, at du fandt jobbet på ofir.dk


    Senior Analog Layout Engineering - Networking

    What you will be doing

    :
  • Strategizing and implementation of high-speed opto-electrical analog layout in state-of-the-art nodes.

  • In close co-operation with the Design Team, review and analyze complex analog schematics for layout implementation.

  • Ensuring that all relevant parasitics are considered and ensuring quality by identifying and verifying device matching, IR drop and electro migration.

  • Potentially planning, ensuring stakeholder management and leading projects from start to finish.

  • What we need to see:

  • Dedication and drive to improve the success of the team.

  • Strong drive and ability to understand the problem and decide on solutions.

  • Systematic approach to planning and execution.

  • A Master’s Degree or equivalent experience in electrical engineering or similar.

  • Minimum of 5 years' experience with Analog IC Layout is required.

  • Ways to stand out of a crowd:

  • Transistor level knowledge for circuits such as TIAs and Optical Drivers.

  • Ability to recognize failure prone circuit and layout structures, good grasp of analog and DFM standard methodologies, and proactivity in working with circuit designers to identify the best approach to solving problems.

  • Knowledge of Mentor, Synopsys or Cadence layout tools.

  • Proactively influence the chip design process by means of automatization and strategizing.

  • Previous responsibility for ramping up new process nodes.

  • Skriv i din ansøgning, at du fandt jobbet på ofir.dk


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